Creating 256 Bytes of RAM (in a simulation)

Let’s try building a whopping 256 bytes of random access memory (inside a digital logic simulation).

This is part 5 of my journey to explore the basics of how computer’s work. If you’d like to watch the other episodes, you can find the full playlist here:
https://youtube.com/playlist?list=PLFt_AvWsXl0dPhqVsKt1Ni_46ARyiCGSq&si=tYFx249Y6Nufctdb

The simulation program is in a slightly rough and unstable state as I’m developing it as I go, but if you’d like to try it out, the latest version (and source code) is available over here:
https://sebastian.itch.io/digital-logic-sim
https://github.com/SebLague/Digital-Logic-Sim

If you’d like to support me in creating more videos, consider becoming a patron of the channel:
https://www.patreon.com/c/SebastianLague

This series was largely inspired by the 8-bit breadboard computer series by @BenEater (so be sure to check that out if you haven’t already)!

Image and music credits:
https://raw.githubusercontent.com/SebLague/Misc-Project-Info/refs/heads/main/Digital-Logic-Sim/ram-credits.txt

Chapters:
00:00 Intro and a New Simulation
01:50 A Grid of Latches
03:12 Decoder
04:42 1-Bit Memory Cell
06:42 Rambling about Dynamic and Static Memory
08:46 16 Bits of Memory
11:41 Surprise Inspection
12:16 256 Bits of Memory
14:28 Asynchronous RAM
18:02 A Brief Note Concerning Caches
19:00 Synchronous RAM
22:28 Equality Chip
23:28 The Final Test
24:37 A Trip Down Memory Lane

source